ds-104 rev e01 saronix nth / nch series saronix crystal clock oscillator technical data 5v, hcmos 141 jefferson drive ? menlo park, ca 94303 usa 650-470-7700 800-227-8974 fax 650-462-9894 500 khz to 106.25 mhz frequency stability: * see part numbering guide frequency range: 20*, 25, 50 or 100 ppm over all conditions: calibration tolerance, operating temperature, input voltage change, load change, 30 day aging, shock and vibration. actual size description a 5v crystal controlled, low current, low jitter and high frequency oscillator with precise rise and fall times demanded in networking applications, such as gigabit ethernet and fibre channel. the tri-state function on the nth enables the output to go high impedance. device is pack- aged in a 14 or an 8-pin dip compatible resistance welded, all metal grounded case, to reduce emi. applications & features fibre channel gigabit ethernet 32 bit microprocessors tri-state output on nth hcmos/ttl compatible smd plastic available 3.3v version available mechanical: shock: solderability: terminal strength: vibration: solvent resistance: resistance to soldering heat: mil-std-883, method 2002, condition b mil-std-883, method 2003 mil-std-883, method 2004, conditions b2 mil-std-883, method 2007, condition a mil-std-202, method 215 mil-std-202, method 210, condition a, b or c ( i or j for gull wing) output waveform 80% v dd 1 level 0 level 50% v dd 20% v dd 2.5 vdc 1.5 vdc 0.5 vdc gnd v dd t r t f t f t r symmetry symmetry cmos ttl environmental: gross leak test: fine leak test: thermal shock: moisture resistance: mil-std-883, method 1014, condition c mil-std-883, method 1014, condition a2 mil-std-883, method 1011, condition a mil-std-883, method 1004 tri-state logic table (nth only) pin 1 input logic 1 or nc logic 0 or gnd pin 8 (5) output oscillation high impedance required input levels on pin 1: logic 1 = 3.0 v min logic 0 = 0.5v max output drive: hcmos symmetry: rise and fall times: logic 0: logic 1: load: rms period jitter: ttl measured @1.5v level, see part numbering guide 6ns max to 24 mhz @ 0.5 to 2.5v 3ns max 24+ to 80 mhz 1.5ns max 80+ to 106.25 mhz 0.5 v max v cc -0.6v min 10ttl to 50mhz, 5ttl 50+ to 106.25 mhz 8ps max measured @50%v dd, see part numbering guide 8ns max to 24 mhz @20% to 80% v dd 5ns max 24+ to 80 mhz 2ns max 80+ to 106.25 mhz 10% v dd max 90% v dd min 50pf to 50mhz, 30pf 50+ to 70 mhz, 15pf 70+ to 106.25 mhz 8ps max symmetry: rise and fall times: logic 0: logic 1: load: rms period jitter: temperature range: operating: storage: supply voltage: recommended operating: +5vdc 10% -55 to +125c 0 to +70c or -40 to +85c supply current: 0.5 to 8 mhz: 8+ to 24 mhz: 24+ to 50 mhz: 50+ to 80 mhz 80+ to 106.25 mhz: 12ma 20ma 35ma 50ma 65ma
ds-104 rev e01 saronix nth / nch series saronix crystal clock oscillator technical data 5v, hcmos 141 jefferson drive ? menlo park, ca 94025 usa 650-470-7700 800-227-8974 fax 650-462-9894 all specifications are subject to change without notice. series nth = tri-state, hcmos compat. nch = pin1 n/c, hcmos compat. n t h 0 6 0 b ? 24.0000 package details part numbering guide 21.0 .825 max 5.08 .200 max .46.08 .018.003 15.24.13 .600.005 12.19.13 .480.005 4.57.13 .180.005 13.0 .510 (4) glass insulators pin 7 gnd pin 8 output half size package max 0.91 .036 full size package pin 1 tri-state - nth n/c - nch max pin 14 +5vdc 7.75 .305 120 120 120 pin 1 tri-state - nth n/c - nch 1.5 .059 13.0 .510 max pin 4 gnd 1.7 .067 pin 8 +5vdc 6.0 .236 pin 5 output 7.62.20 .300.008 7.62.20 .300.008 5.08 .200 max .46.08 .018.003 0.91 .036 max 10.87 .428 max 13.0 .510 max saronix saronix marking format ** includes date code, frequency & model denotes pin 1 6.35.51 .250.020 6.35.051 0.250.02 scale: none (dimensions in ) mm inches denotes pin 1 ** exact location of items may vary marking format ** includes date code, frequency & model test circuits ma m power supply v m oscillator pin 14 (8) test point pin 8 (5) v cc out gnd pin 7 (4) pin 1 (1) * tri-state input (nth only) note a: c l includes probe and fixture capacitance *( ) indicates pin numbers for half-size package hcmos (used at saronix) c l = see specs on previous pg (note a) pin 14 (8) v m test point v cc out oscillator pin 8 (5) gnd pin 7 (4) pin 1 (1) * power supply ma m c l = 15 pf (note a) r l = 390 ? mmbd7000 or equiv tri-state input (nth only) note a: c l includes probe and fixture capacitance *( ) indicates pin numbers for half-size package ttl (optional load) frequency (mhz) symmetry / temperature range 0 = 40/60%, 0 to +70 c 2 = 40/60%, -40 to +85 c 4 = 45/55%, -40 to +85 c, 0.5 to 40 mhz only (ttl) 6 = 45/55%, 0 to +70 c, 0.5 to 50 mhz only (ttl) a = 45/55%, 0 to +70 c, 0.5 to 70 mhz only (cmos) c = 45/55%, -40 to +85 c, 0.5 to 50 mhz only (cmos) frequency range 3 = 0.5 to 6 mhz 6 = 6+ to 24 mhz 8 = 24+ to 106.25 mhz stability tolerance c = 100ppm b = 50ppm a = 25ppm, 0 to +70 c only aa = 20ppm, 0 to +70 c only, 80mhz max package 0 = full size, thru hole 9 = half size, thru hole k = full size, gull wing j = half size, gull wing n = half size, gull wing, spanked leads example pn: nth030c-6.0000 max
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